On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model

Logic-level simulation is still one of the most often used operations on digital designs during both design and test stages. This makes it a critical issue affecting the overall cost of a project. In this paper we investigate and show the origins of common advantages of four recently proposed efficient simulation methods of different classes: logic simulation, multi-valued simulation, timing simulation, and fault simulation. Described advantages became possible due to use of a highly efficient model called Structurally Synthesized Binary Decision Diagrams (SSBDD). This very compact model preserves the structural information about the modeled circuit and utilizes circuit partitioning into a set of macros represented each by its own SSBDD. All this makes the SSBDD model a good choice as a logic-level digital design representation. The analysis is made on the basis of experimental data acquired using ISCAS’85 benchmark circuits.